EFM32G-DK3550【PDF 274/467 页】KIT DEVELOPMENT EFM32 GECKO

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...the world's most energy friendly microcontrollers

Bit

Name

Reset

Access

Description

Set time span for the rising edge.

Value

DTRISET

Description

Rise time of DTRISET+1 prescaled HFPERCLK cycles

7:4

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

3:0

DTPRESC

0x0

RW

DTI Prescaler Setting

Select prescaler for DTI.

Value

0

1

2

3

4

5

6

7

8

9

10

Mode

DIV1

DIV2

DIV4

DIV8

DIV16

DIV32

DIV64

DIV128

DIV256

DIV512

DIV1024

Description

The HFPERCLK is undivided

The HFPERCLK is divided by 2

The HFPERCLK is divided by 4

The HFPERCLK is divided by 8

The HFPERCLK is divided by 16

The HFPERCLK is divided by 32

The HFPERCLK is divided by 64

The HFPERCLK is divided by 128

The HFPERCLK is divided by 256

The HFPERCLK is divided by 512

The HFPERCLK is divided by 1024

19.5.18 TIMERn_DTFC - DTI Fault Configuration Register

Offset

0x078

Reset

Access

Name

Bit Position

Bit

Name

Reset

Access

Description

31:28

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

27

DTLOCKUPFEN

0

RW

DTI Lockup Fault Enable

Set this bit to 1 to enable core lockup as a fault source

26

DTDBGFEN

0

RW

DTI Debugger Fault Enable

Set this bit to 1 to enable debugger as a fault source

25

DTPRS1FEN

0

RW

DTI PRS 1 Fault Enable

Set this bit to 1 to enable PRS source 1(PRS channel determined by DTPRS1FSEL) as a fault source

24

DTPRS0FEN

0

RW

DTI PRS 0 Fault Enable

Set this bit to 1 to enable PRS source 0(PRS channel determined by DTPRS0FSEL) as a fault source

23:18

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

17:16

DTFA

0x0

RW

DTI Fault Action

Select fault action.

Value

0

1

2

Mode

NONE

INACTIVE

CLEAR

Description

No action on fault

Set outputs inactive

Clear outputs

2011-04-12 - d0001_Rev1.10

274

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